| 摘要 |
PURPOSE:To generate a clock signal of a same phase even when a clock signal sent through a clock line is delayed. CONSTITUTION:The synchronization type circuit operating circuit components synchronously with each other based on a clock signal led from a common clock line is provided with a couple of clock lines La, Lb looped back on the way and with means M1-M3 generating a clock signal CLK0 having an intermediate phase of two clock signals based on the two clock signals (CLK1, CLK6), (CLK2, CLK5), (CLK3, CLK4) with a different phase obtained from an optional point on a couple of the clock lines La, Lb at an equal distance when viewing from a turn-over point P0 on a couple of the clock lines La, Lb. Three clock signals CLK0 are all in phase because the two clock signals with a different phase at an equal distance point from the turning point PO are used. |
