| 摘要 |
PURPOSE:To promote the efficiency of a BUS by transferring data without using the BUS in respect of data transfer between circuits to execute the data transfer frequently. CONSTITUTION:An exclusive data line 6 and a selection circuit 7 are installed in an interval between, for instance, a RAM 1 and an arithmetic circuit 2 where the data transfer is executed frequently. Thus, at the same time as the data transfer from the RAM 1 to the arithmetic circuit 2 is executed, the data transfer can be executed between other units, i.e., a register 3 and the register 4 as well. Besides, at the same time as the data transfer from the RAM 1 to the arithmetic circuit 2 is executed, the result of arithmetic operation can be transferred from the arithmetic circuit 2 to the register 3 or the register 4. |
