| 摘要 |
<p>PURPOSE:To suppress a generated instantaneous current by providing at least two gates or over of an inverter section to an inside of an I/O cell when the I/O cell of a peripheral circuit section of a gate array is set for the output so as to switch gates closest to an output pad from a high level to a low level or vice versa simultaneously. CONSTITUTION:A wiring layout is decided so that number of inverters of at least two signal line I/O cells differs from one bus at design. An I/O cell 9 of a BUS 15 uses all of 7-stages of inverters an I/O cell 6 of a BUS 1 uses series connection of three stages of inverters. An I/O cell 5 of a BUS 0 employs 1-stage of inverter. In this embodiment, 7 inverters are arranged in one I/O cell and number of gate stages through which output signals BUS 0-15 from an LSI chip core pass till they are outputted to the outside of the chip is selectable for 1, 3, 5, 7 stages depending on a metallic wire. Thus, an instantaneous current is dispersed.</p> |
