发明名称 |
Non-volatile semiconductor memory device incorporating data latch and address counter for page mode programming |
摘要 |
A column latch and a high voltage switch connected to each bit line are eliminated, and an address counter and the data latch are newly provided. The data latch is arranged between an I/O buffer and a Y gate. In a programming cycle, the address counter is activated and transfer gates in the Y gate are successively selected. Consequently, a high voltage Vpp or 0 V is applied periodically to bit lines in the memory cell array in accordance with the write data stored in the data latch.
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申请公布号 |
US5363330(A) |
申请公布日期 |
1994.11.08 |
申请号 |
US19920826943 |
申请日期 |
1992.01.28 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
KOBAYASHI, SHINICHI;NAKAYAMA, TAKESHI;MIYAWAKI, YOSHIKAZU;FUTATSUYA, TOMOSHI;TERADA, YASUSHI |
分类号 |
G11C16/10;G11C16/12;(IPC1-7):G11C16/02 |
主分类号 |
G11C16/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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