| 摘要 |
<p>PURPOSE:To obtain the semiconductor integrated circuit provided with a delay circuit small in layout area and low in current consumption by constituting a resistor means of a MOS transistor (TR) and applying an intermediate potential to a gate electrode. CONSTITUTION:The integrated circuit is provided with a resistor means 105 having a p-channel MOS TR 105a and an n-channel MOS TR 105b connected between a 1st node 104 and a 2nd node 106 receiving a signal having a binary level of a 1st potential and a 2nd potential whose gate electrode receives an intermediate potential between the 1st potential and the 2nd potential. The p-channel MOS TR 105a and the n-channel MOS TR 105b are not fully conductive to increase the resistance between the 1st node 104 and the 2nd node 106. Then a resistor means 105 is formed by the two TRs being the p-channel MOS TR 105a and the n-channel MOS TR 105b to reduce a layout area.</p> |
