| 摘要 |
A logic simulator having plural logic function sections for realizing a logic circuit, plural connection sections for connecting these logic function sections, a control section for constructing a logic simulation circuit by controlling these logic function sections and connection sections, and a host computer as an interface and a controller of the logic simulator. Each logic element includes a memory for storing information to decide a logic function, another memory for storing other control information. A logic element having a PLA where each logic to be realized is developed by an AND plane and the result is obtained through an OR plane based on predetermined information. A logic element having a universal logic gate, the input terminals of the universal logic gate being respectively connected to the input terminals of the logic element through plural switches. A unit-delay multiples logic element having a sampling hold circuit including a specification section for specifying only one pulse signal from a multiplexed input signal, a sampling section for sampling a pulse signal specified by the specification section at a predetermined simulation cycle, and a hold section for holding a pulse signal sampled by the sampling section and converting the pulse signal into a restoration signal having a constant level at start of a new simulation cycle, a logic circuit for giving a predetermined logic operation to the restoration signal, and a pulse circuit for producing a multiplexable pulse signal from a signal processed by the logic circuit.
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