Method and system for ensuring interconnect integrity in a micro-chip-module

摘要

The integrity of the interconnects in a predefined micro-chip-module are tested in two phases. Before any integrated circuit chips are loaded onto the micro-chip-module, the capacitance value of each interconnect is measured and the measured capacitance value is compared with a predetermined range of acceptable values to establish if an interconnect error exists. The measurement and comparison process is repeated after a predefined set of integrated circuit chips are loaded onto the micro-chip-module. The capacitance of each interconnect node is indicative of the total length of the interconnect traces of the node, and thus a short circuit will result in a capacitance measurement above the predetermined range for the node, and an open circuit will result in a capacitance measurement below the predetermined range for the node. In addition, the relationships between the capacitances of the nodes before and after loading the chips on the micro-chip-module can be represented by a set of equations, and those equations can be used to define the range of acceptable capacitance values for each node of the loaded micro-chip-module as a function of the capacitances of the input/outputs of the chips loaded onto the micro-chip-module.