| 摘要 |
PURPOSE:To stably attain operating a phase locked loop by providing preset values as many as the number of frequencies existing even when plural frequencies exist in a reference signal. CONSTITUTION:When power source turned ON frequency division values T1, T2 are set respectively to registers 31, 32 through signal lines L31, L32 by a control part. The output signal lines L33, L34 of the registers 31, 32 are connected to a selector 26, and the selector 26 is operated so that the signal on the signal line L33 or the signal line L34 appears on the signal line 35 by a control signal (vertical synchronizing signal VD). For instance, when the synchronizing signal VD is logic 1, the frequency division value T1 of the register 31 is outputted to the signal line 35 through the signal line L33 and the selector 26 to be set to a frequency divider 24. Further, when the control signal (vertical synchronizing signal VD) is logic 1, the frequency division value T2 of the register 32 is selected by the selector 24 to be set to the frequency divider 24 through the signal line L34 and the selector 26. |
