| 摘要 |
PURPOSE:To shorten computing time by outputting a computed result up to the time of a high-order part at a time when a carry signal on a low-order side is decided. CONSTITUTION:The computation of two carry signals when the carry signal from a low-order part Z10 exists and not are performed on the least significant bit Z by an output switching type full adder 6, and also, the computation of the sum signal of the two carry signals when the carry signal exist and not is performed. Also, two carry signals are outputted from the high-order parts Z12-Z14 higher than that by computing each carry signal at each digit by using the two carry signals from the low-order part, and also, the computation of the sum signal of its own digit is performed by the two carry signals. The computation of the sum signal of its own digit is performed at a most significant part Z15 by using the two carry signals from the low-order part Z14. When the carry signal at the low-order part Z10 is decided, the carry signal is fetched in the high-order parts Z11-Z15, and either sum signal of its own digit is outputted corresponding to the carry signal. |
