| 摘要 |
<p>PURPOSE:To obtain the clock generating circuit whose variation of jitters is minimized by shifting a synchronizing signal, which possibly has jitters, by a shift register, and extracting an output signal whose timing is the closest to the mean value from plural outputs and inputting it to PLL circuit. CONSTITUTION:The horizontal synchronizing signal 1 having jitters as fluctuations of timing pulses is inputted to the shift register 2 and then shifted in order with the clock of the VCO output 3 of the PLL circuit and the output signal is sent to output terminals 12, 13, 14... in order. This output is inputted to an encoder 5 and converted into a binary number, and the code is inputted to a latch 6, latched with the output (system clock) 11 of the PLL circuit, and sequentially inputted to and stored in a mean value calculating circuit 7 to calculate the mean value. Then the current mean value of the horizontal synchronizing signal and this value are inputted to a parameter adjuster 9 and the horizontal synchronizing signal which is the closest to the mean value is selected among the outputs 12, 13, 14... of a delay element 2 and inputted to the PLL circuit.</p> |
