| 摘要 |
PURPOSE:To extract a sampling clock at an optimum data sampling place at low cost by shifting the phase of a bit synchronous clock from an oscillation means in accordance with a phase difference detected in a phase comparator. CONSTITUTION:A phase difference voltage conversion circuit 4 and a phase shifter circuit 5 are cascade-connected to the output-side of the phase comparator 1. The output signal of VCO 3 is supplied to the phase shifter 5 and the sampling clock for data sampling is fetched from the circuit 5. The phase comparator 1 compares a reception signal with the clock phase of VCO 3 and detects a phase difference signal. A loop filter 2 restricts the frequency band of the detected phase difference signal. The oscillation frequency is controlled by an output signal from the loop filter 2 in VCO 3. Following speed for the change of the phase in the PLL circuit is adjusted by the loop filter 2. |
