| 摘要 |
PURPOSE:To prevent a frequency jump at frequency changeover with respect to the phase locked type frequency synthesizer provided with a variable frequency divider with a phase locked loop type reset. CONSTITUTION:A variable frequency divider 13 generates a signal of a frequency division frequency from an output of a VCO 6 and a variable frequency divider 20 with phase locked loop type reset releases a reset of a variable frequency divider 24 with reset in a timing of a signal of a division frequency at rising of a control signal to frequency-divide a reference clock resulting in generating a signal of a reference frequency, a phase comparator 4 obtains a phase error between the signal of the reference frequency and a signal of the divided frequency, a loop filter 5 applies time integration to a phase error output to generate a control voltage, the VCO 6 generates a signal of the output frequency in response to a control voltage to interrupt input of both signals to the phase comparator 4 and provides the control voltage corresponding to a new frequency to an integration capacitor 19 to switch the frequency, then the release of reset of the variable frequency divider 20 with phase locked loop reset is delayed from the initial timing. |
