| 摘要 |
PURPOSE:To prevent deteriorated stability due to much more jitter in a VCO output when lots of '0s' are in existence in an data input in the PLL circuit (in the case of a small mark rate) and to increase '0' consecutive strength against the data input. CONSTITUTION:A '0' detection circuit 6 detects '0s' of a data input 1 to generate a '0' detection signal. An output voltage of an LPF 4 for a just preceding period is sampled by a sample-and-hold circuit 7 for a presence period of the '0' detection signal to obtain a control input of the VCO 5. When the data input is other than '0' (for '1'), the sample-and-hold circuit 7 is not operated and an LPF output is used for the VCO control input as it is. |
