发明名称 CLOCK SIGNAL CUT DETECTION CIRCUIT
摘要 <p>PURPOSE:To make a detection circuit into LSI and to clarify the value of detection time and an error range by using an input clock signal becoming an object and a counter clock for detection time decision. CONSTITUTION:When the input clock signal CLK 1 is cut, a counter 11 detects an H level and a counter 21 detects an L level. In the case of H-impedance, the level is decided to H by pulling up R1 input. Furthermore, clock signal cut detection time T can be decided by the frequency F of a clock signal CLK 2 and the load value L of the counter. Namely, it becomes T=(L-1)/F+DELTAT. Here, DELTAT is the error range and the maximum value is 1/F. Thus, detection time and the error range can precisely be decided, the circuit can be made by a digital circuit and the circuit can be made into LSI.</p>
申请公布号 JPH06311150(A) 申请公布日期 1994.11.04
申请号 JP19930100997 申请日期 1993.04.27
申请人 OKI ELECTRIC IND CO LTD 发明人 TEZUKA KAZUTO
分类号 G06F1/04;H04L7/00;(IPC1-7):H04L7/00 主分类号 G06F1/04
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