发明名称 OPERATION SUPERVISORY UNIT OF DIGITAL COMPUTER
摘要 PURPOSE:To inhibit next address writing to a microprogram address register when a fault is detected by checking a microprogram read out from a control memory unit before it is written to a latch register. CONSTITUTION:Before being written to latch register ML, a microprogram read out from control memory unit CROM is checked by microprogram error check circuit CHK. If a fault occurs, FF is set and a write pulse to microprogram memory address register MPR is cut off via inhibition gate G. In this way, if control memory part CROM is in trouble, it is detected and microprogram address register MPAR is frozen at a fault-element position, so that the information can be given by supplying it to IND2.
申请公布号 JPS5510641(A) 申请公布日期 1980.01.25
申请号 JP19780082947 申请日期 1978.07.10
申请人 HITACHI LTD 发明人 NOMURA SEISHI;KAWAMATA YASUO
分类号 G06F11/08;G06F11/00 主分类号 G06F11/08
代理机构 代理人
主权项
地址