System for optimizing argument reduction.

摘要

In a processor comprising: a) a first block operative to perform pipeline ADD/SUB/COMPARE operations on argument mantissa including: a first adder (37), an aligner (44), a first output register (39, TR3M) whose most significant bit is the carry-out bit generated by the first adder (37), the output of said first block being connected to a normalizer (40), a leading zero detector/encoder (41), and a second output register (23, TR5M), b) a second block operative to perform pipeline ADD/SUB/COMPARE operations on argument exponents, including a second adder (36) and a third output register (38, TR3E) whose output is connected to an encoder (43) controlling the aligner (44), c) a third block operative to perform pipeline MULTIPLY operations on argument mantissa including a multiplier (22), whose outputs are fed back into the inputs of the first adder (37), and d) a stacker (35) to pipeline arguments and a memory (24) for providing input constant values to respectively first, second and third block, a system for optimizing argument reduction to a value comprised between 0 and a multiple of PI comprising: a fourth output register (25, TR5E) being connected to the output of the second adder (36), means (28) for allowing the encoder (43) to also control the normalizer (40), and means (26, 27) for allowing the second output register (23, TR5M) to shift its content by a number of bits, and input the same number of bits from the first adder (37) as its most significant bits. <IMAGE>