| 摘要 |
A plurality of address transition detecting sub-units (28A/ 28B) incorporated in a semiconductor memory device monitors address bits to see whether or not at least one address bits is changed in logic level for producing an address transition signal (ATD) from the output signals (ATDA/ ATDB) of the respective address transition detecting sub-units, and a plurality of charging transistors (Qp13/ Qp14) coupled in parallel between a power voltage line (Vcc) and a decoding line (270e) are respectively gated by the output signals of the address transition detecting circuits for charging the decoding line to a precharged level so that a decoding circuit (270d) quickly determines whether or not the stored address is matched with the address represented by the address bits for replacing a defective column of regular memory cells with a column of redundant memory cells. <IMAGE> |
