| 摘要 |
A synchronous counter circuit comprises first and second counting circuits and a latch circuit. Each of the first and second counting circuits includes a clock terminal for receiving a clock signal, an enable terminal for receiving an enable signal, a counter coupled to the clock terminal for counting pulses of the clock signal, a carry signal generating circuit coupled to the counter for generating a carry signal in response to a finish of the counting of the counter, and a ripple carry signal generating circuit coupled to the clock terminal and the carry signal generating circuit for generating a ripple carry signal in response to the clock signal and the carry signal. The latch circuit is coupled to the carry signal generating circuit and the ripple carry signal generating circuit of the first counting circuit for generating another enable signal in response to the carry signal and the ripple carry signal which are output from the carry signal generating circuit and the ripple carry signal generating circuit of the first counting circuit. The latch circuit has an output terminal coupled to the enable terminal of the second counting circuit.
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