| 摘要 |
The basic concept of the present invention comprises converting a standard buffer circuit into an adjustable buffer circuit that will in effect reduce the operating speed and power consumption of the IC in which it is constructed. An adjustable buffer circuit can be designed into a chip design that will allow manufacturing to either use a bonding option or the blowing of a fuse to adjust its operating speed and active power consumption. One important application would be in memory devices such as for static random access memory (SRAM) devices. For example, if may be desirable to allow a -15 ns access time SRAM to be downgraded to a -20 ns or -35 ns access time device while lowering its active power consumption by APPROX 20-30% so that it will pass the -35 ns ICC specification rating. Although the concept of the present invention would require more layout area on the die, by appropriately bonding or blowing a fuse to control the adjustable circuitry, slower speed grades that meet power rating specifications are obtained.
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