| 摘要 |
PURPOSE:To speed up the operation of the integrated circuit device which has a sequential circuit and to increase the margin of phase locking for the data processing of the sequential circuit. CONSTITUTION:An integrated circuit 50 is provided with the phase locked loop circuit 57 and a clock signal CK7 which is inputted from outside through the phase locked loop circuit is supplied to the sequential circuit 52. Data outputted by the sequential circuit 52 are fed back to the phase locked loop circuit 57 from the output terminal of a buffer Bu 56. The sequential circuit 52 compares the phase of the clock signal CK7 inputted through the buffer Bu 50 with the phase of the output data of the sequential circuit 52 and adjusts the phase of the clock signal outputted to the sequential circuit 52 so that they are in phase with each other. The output data DO7 outputted from the sequential circuit 52 are never delayed to the clock signal CK7. Consequently, the integrated circuit 70 can process the data at a high speed. |
