| 摘要 |
PURPOSE:To considerably reduce the amount of data treated as errors by making a number of external reset signals in coincidence with that of a normal state. CONSTITUTION:A block length counter 21 is reset by means of a synchronization detecting signal and an interpolation synchronizing signal from a gate circuit 12 and counts the interval of synchronized patterns in an input data train. Decoders 22, 23, 25 decode the count value of the block length counter 21 and generate a first window pulse, a second window pulse and an interpolation synchronizing signal. A gate circuit 24 performs the gating the synchronization detecting signal by means of the second window pulse. An OR circuit 26 obtains the OR of the synchronization detecting signal and the interpolation synchronizing signal subjected together to gating and outputs as external reset signal as the reference of deinterleave. |
