发明名称 TESTING CIRCUIT FOR ADDING CIRCUIT
摘要 PURPOSE:To provide the testing circuit for exerting no influence on a speed of a regular operation of an adder. CONSTITUTION:The testing circuit is provided with selectors 21-28 for selecting one of each of input data A, B and each of test data X, Y, selectors 31-38 for selecting one of each of output data from the selectors 21-28 and test data Z and supplying it to input terminals (a), (b) of each of full adders 11-14, respectively, and a test control circuit for supplying the test data X, Y and Z, and also, supplying switching signals K1-K3 for controlling a selecting operation of the selectors 21-28, 31-38.
申请公布号 JPH06301518(A) 申请公布日期 1994.10.28
申请号 JP19930083186 申请日期 1993.04.09
申请人 NEC CORP 发明人 NAKAJIMA HIROYUKI
分类号 G06F7/499;G06F7/50;G06F11/22 主分类号 G06F7/499
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