SELF-CALIBRATION TECHNIQUE FOR HIGH-SPEED TWO-STAGE AND PIPELINED MULTI-STAGE ANALOG-TO-DIGITAL CONVERTERS

摘要

The self-calibration technique presented in this disclosure is designed for high-speed twostage and pipelined multi-stage A/D converters (ADCs), and n is absolutely unique in world-wide literature or markets at the time of this application. The technique is found to be very helpful in improving the conventional design of the ADCs toward higher speed, lower power dissipation and smaller device size by reducing stringent component-mismatching requirement in designing very large scale integration (VLSI) ADC chips. The technique provides a non-switched-capacitor (nonSC) robust alternative for VLSI implementation of critical parts in two-stage and pipelined multistage ADCs. The technique comprises an adaptive offset shaping technique for flash A/D subconverters (ADSCs) of all stages and residue-based error correction technique for digital-to-analog subconverters (DASCs) of all stages in two-stage or pipelined multi-stage ADCs. The critical part of the adaptive offset shaping technique for ADSCs is an adaptive self-trimming process. The self-trimming process is delta-modulation based, and is carried out at each time instant by adjusting voltage thresholds of two successive comparators in an ADSC when digital output from the lower one is set to HIGH. Gain error in interstage sample-and-held amplifier (SHA) of a twostage or pipelined multi-stage ADC can be automatically counteracted during the threshold selftrimming. The residue-based error correction technique uses overflow/underflow code information obtained from quantizing a residue signal from each previous subconversion stage of a two-stage or pipelined multi-stage ADC, and the threshold errors of ADSC and DASC in the previous stage are corrected solely based upon overflow and underflow of the residue signal.