CLOCK GENERATING CIRCUIT

摘要

PURPOSE:To generate a reference clock with high stability by eliminating noise generated in a PLL circuit when the reference clock is generated through the use of the PLL circuit. CONSTITUTION:The clock generating circuit 4 is provided with three PLL circuits 10A,10B,10C connected in common to one clock input terminal IN and a majority decision circuit 20 whose three input terminals I1-I3 receive output signals O1-O3 of the PLL circuit. When two levels or over in the input terminals I1-I3 are coincident, the majority decision circuit 20 outputs a signal of the level through an output terminal OUT. Thus, even when noise is invaded in the output signal of the PLL circuit and when outputs of the other PLL circuits are coincident, the coincident signal is outputted as a clock signal. Moreover, the three PLL circuits are provided with delay elements 14a-14c whose delay time differs. Thus, even when noise takes place simultaneously in the PLL circuit, a signal delayed by a different time is outputted from each output terminal and the appearance of the noise from the output terminal OUT is not caused by the operation of the majority decision circuit.