| 摘要 |
PURPOSE:To secure the correction for the code error featuring the highest occurrence frequency by memorizing the data equivalent to the adjacent two clocks through the bipolar PCM code decoder circuit and then opening the gate by these two output ot generate the detection signals when the code error occurs. CONSTITUTION:The level comparison is carried out via comparator 1 and 2 between reference voltage VR1/VR2 and PCM reception signal S in order to obtain the + and - code output. These code output are then applied to n-nit shift register 3 consisting of n-units of D-FF to which timing extracting clock pulse (c) is applied. For the bipolar PCM code, the same code of 1 or - never continues by more than two clocks. Thus, in case the output of NAND gate 4 to which every adjacent two bits are supplied is O, some error exists to produce error detection information (e). When this signal is delivered from gate 4 or 4', corresponding FF5 and 5' are cleared forcedly to secure the output of O. Thus, the error can be corrected. |
