| 摘要 |
PURPOSE:To satisfy a broad capture range, a narrow band and a low steady- state phase deviation simultaneously in the PLL circuit by providing two loops having a high phase comparison frequency and a low phase comparison frequency and selecting the response speed of the loop whose phase comparison frequency is low to be higher than that of the loop whose phase comparison frequency is high. CONSTITUTION:A phase comparator 2 detects a phase difference between an input clock and a clock resulting from frequency-dividing an output clock at a 1/N frequency divider circuit 7 in a loop I. On the other hand, a phase comparator 10 detects a phase difference between an input clock subjected to 1/M frequency division and a clock resulting from NXM frequency-dividing an output clock in a loop II. Then the detected differences are added via LPFs 3,11 and the sum is fed to a VCO 5 to apply frequency control to the output clock. The loop II is dominant when the PLL is in the transient state by setting the response speed of the loop II sufficiently higher than that of the loop I, the capture range is set wider and a narrower band is attained. On the other hand, in the steady-state, the loop I is dominant and a steady-state phase deviation is reduced. |
