| 摘要 |
A system for securing a bus for a multi-processor system includes a plurality of processors connected in a closed loop so that each processor has a bus arbitration input signal output from the preceding processor and a bus arbitration output signal output to the following processor. The processor is judged to have the right to secure the bus when an exclusive logical sum of the bus arbitration input and output signals is a logical "1" and to have no right to secure the bus when the exclusive logical sum is a logical "0". The processor, when it is judged to have the right to secure the bus, reverses its bus arbitration output signal so as to abandon its own right to secure the bus and transfer the right to secure the bus to the following processor.
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