| 摘要 |
A fast TTL to CMOS level converting circuit with reduced standby current is disclosed. A fast first stage CMOS inverter with skewed transistor size ratios is isolated from a large load capacitance by a second inverter. The second inverter connects to the power supply through a depletion mode NMOS transistor. The gate terminal of the depletion mode NMOS transistor is driven by the output of the first inverter. The depletion NMOS disconnects the PMOS transistor of the second inverter from the power supply when the input voltage ranges between the power supply and 2.0 volts, resulting in zero standby current for the second stage. Therefore, the second stage can be made large enough to drive large fanout capacitances without incurring additional standby current.
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