| 摘要 |
A high speed bus system of the present invention features generating first (SYSCLK) and second (TURBOCLK) clock signals, the first clock signal being at a first frequency and the second clock signal being at a second frequency greater than the first frequency. A first industry standard (ISA CLOCK DIVIDER) input bus to which peripherals to operate at the first clock signal frequency and asecond high speed (TURBO CLOCK DIVIDER) bus to which peripherals to operate at the second clock signal frequency are also provided, the peripherals connected to the second high speed input bus operating at a higher speed than the peripherals connected to the first industry standard input bus. Further, a program decoder identifies which peripherals are connected to the second high speed input bus. By utilizing such a system, the present invention allows high speed peripherals to run at their high speeds while other standard speed peripherals run at their standard speed. The present invention achieves this operation in the same system without requiring the high speed peripherals to have any special redesigning. |
