| 摘要 |
The method resolves situations of uncertainty produced by asynchronisms in digital logic simulators arising when a first flip-flop in an input stage receives an incoming signal that can switch inthe time of uncertainty defined by the set-up and hold times associated with an active clock edge. The method consists of a stage of evaluation (1) of the output state of the first flip-flop generated by the digital logic simulator itself; a stage of asynchronism indication (2), which indicates if there is asynchronism or not; a stage or reassignment (3) which, when there has been no asynchronism, assignes the flip-flop with the same state as it had in the previous clock cycle; a stage of assignment (4) of a valid output state when asynchronism has been recognised; and a stage of detection (5) indicating end of simulation in order to return to the first stage of evaluation (1) or to proceed to a finalisation stage (6) of the process. |
