发明名称 ARITHMETIC LOGIC CIRCUIT
摘要 The circuit improves the productivity by addition of signal combination without circuit change. The circuit includes transmission gates (T1-T4), input terminals of transmission gates (T5-T8) which connects minterm input terminals (M1-M4) to transmission gates (T5-T8), control terminals (g1,g2,/g3,/g4),(g5,/g6,g7, /g8) of transmission gates (T1-T4)(T5-T8) which connect to input terminals (A)(B), control terminals (/g1,/g2,g3,g4),(/g5,g6,/g7,g8) of transmission gates (T1-T4), (T5-T8) which are commonly connected with inverters (I11),(I12), and output terminals of transmission gates (T5-T8) which connects to an output terminal(I0).
申请公布号 KR940010672(B1) 申请公布日期 1994.10.24
申请号 KR19920014124 申请日期 1992.08.06
申请人 GOLDSTAR ELECTRON CO., LTD. 发明人 KIM, HYONG - JE
分类号 H03K19/00;(IPC1-7):H03K19/00 主分类号 H03K19/00
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