发明名称 CLOCK REDUNDANCY SWITCHING SYSTEM
摘要 PURPOSE:To prevent a data error for an equipment by absorbing a hit of a clock signal and a phase fluctuation at switching of clock redundancy. CONSTITUTION:A reception clock from a clock supply device is converted into a TTL level by level conversion section 1-1, 2-1 of clock reception panels 1, 2 in duplicate and 6 SEL 3-1 of a switching control panel 3 selects the received clock. A PLOGEN 3-6 generates a PLO phase comparison frequency from the selected reception clock. The PLO1-3, 2-3 of the clock reception panels 1, 2 of each system are operated by the entirely same PLO phase comparison frequency to obtain POL outputs of a same phase in each system.
申请公布号 JPH06296172(A) 申请公布日期 1994.10.21
申请号 JP19930072720 申请日期 1993.03.31
申请人 NEC CORP 发明人 HIRANO KENGO
分类号 H04L1/22;G06F1/04;H04L7/00 主分类号 H04L1/22
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