| 摘要 |
PURPOSE:To surely detect a synchronizing signal even when the DC component recovery is inaccurate by utilizing a high-order 2-bit of a digital conversion signal when a threshold level is set to a synchronizing signal of a frame pulse train. CONSTITUTION:A base band signal of 2VP-P is inputted to an input terminal 100, the DC component is cut off by a capacitor 2 and the result is fed to a clamp circuit 3. The output of the clamp circuit 3 is subject to A/D conversion 4 in the timing of a clamp pulse (CP) to attain 8-bit constitution. The high-order 2-bit (1st MSB and 2nd MSB) are subject to pattern discrimination 501, 502, its output is ORed (503) and inputted to an external frame pulse (FP) generating circuit 504 to generate the frame pulse, that is, an external synchronizing signal, which is inputted to an FP phase comparator 6. Even when the frame synchronization is unlocked and the DC component recovery is faulty, the 2nd MSB repeats '0', '1' at the 25, 50, 100% of the video level. Thus, even when the DC component recovery is inaccurate, the synchronizing signal is detected surely. |
