发明名称
摘要 PURPOSE:To prevent the generation of a reading error even when the contents of a memory cell connected to a bit line arranged to the neighbour of an aluminum wiring are read by making a distance between the wiring and the bit line disposed to the neighbour of the wiring the same as that between bit lines. CONSTITUTION:The shape of the side of an aluminum wiring 7 is equalized to the shapes of the sides of bit lines BLn-1--BLn, and the width of the aluminum wiring 7 is made equal to the width of the bit lines BLn-1--BLn. The aluminum wiring 7 is disposed so that a distance between the wiring 7 and the bit line BLn or -BLn is equalized to a distance between bit lines. Since the line-to-line capacitance of the bit line arranged to the neighbour of the aluminum wiring formed into a memory cell array is made approximately equal to the line-to-line capacitance of another bit line, the capacitance of several bit line in the memory cell array can be equalized approximately. Accordingly, no error is generated even when the memory contents of a capacitor for a memory cell connected to the bit line disposed to the neighbour of the aluminum wiring are read.
申请公布号 JPH0682802(B2) 申请公布日期 1994.10.19
申请号 JP19850110942 申请日期 1985.05.23
申请人 MITSUBISHI ELECTRIC CORP 发明人 MYAMOTO HIROSHI
分类号 G11C11/401;H01L21/3205;H01L21/8242;H01L23/52;H01L27/01;H01L27/10;H01L27/108 主分类号 G11C11/401
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