发明名称
摘要 A charge amplifying memory cell and its method of making based on trench technology. A trench is formed which reaches through an n-type well region (32) to a p<+>-type substrate (30). A triple layer (36, 38, 40) is formed on two sidewalls of the trench consisting of two capacitive insulating layers and a intermediate p<+> polysilicon layer. The trench is then at least partially filled with a conductor, such as polysilicon (42), facing the triple layer. Thereby, the intermediate polysilicon layer acts as a charge storage node with capacitance to both the substrate and the polysilicon filling the trench. The insulating layer facing the well is opened with a contact hole near its top so that a p<+> transistor drain (44) is formed in the adjacent well by diffusion from the polysilicon through the contact hole. A p<+> transistor source (50) is doped into the well with a gate region between it and the drain to provide a write transistor. A p+ region (46) is also formed adjacent a sidewall of the trench other than the one containing the contact hole so that a read transistor is vertically formed in the n-type well between it and the substrate. The intermediate p<+> polysilicon layer acts as the electrode of this read transistor, whereby stored charge is amplified by the read transistor.
申请公布号 JPH0682793(B2) 申请公布日期 1994.10.19
申请号 JP19890010102 申请日期 1989.01.20
申请人 INTAANASHONARU BIJINESU MASHIINZU CORP 发明人 DONARUDO MAKUARUPIN KENII
分类号 G11C11/405;H01L21/8242;H01L27/108 主分类号 G11C11/405
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