发明名称
摘要 PURPOSE:To reduce and simplify the manufacturing process by forming a bi- polar element and a junction FET at the same time. CONSTITUTION:N<+> buried diffused layers 102 and 202 are formed in a P type semiconductor substrate 1, and the collector layer 103 of the bi-polar transistor 100 and the back gate 203 of the junction FET200 by growth of epitaxial layers. Boron is selectively ion-implanted and heat-treated, thus forming selective oxide films 110 and 210, an external base layer 106, a source 206, and a drain 206. Then, a polycrystalline Si film doped with an N type impurity is formed by boron ion implantation and then heat-treated, resulting in the formation of an emitter layer 109, an internal base layer 107, a top gate 209, and a channel layer 207. Thereafter, each electrode is formed, and accrodingly the transistor 100 and the junction FET200 are formed.
申请公布号 JPH0682789(B2) 申请公布日期 1994.10.19
申请号 JP19830197155 申请日期 1983.10.20
申请人 ROHM KK 发明人 TAKASU HIDESHI
分类号 H01L29/808;H01L21/331;H01L21/337;H01L21/8222;H01L21/8248;H01L27/06;H01L29/73;H01L29/732;H01L29/80;(IPC1-7):H01L27/06 主分类号 H01L29/808
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