| 摘要 |
PURPOSE:To provide a digital signal processing system capable of transmitting/ receiving digital signals for which a hardly decodable scramble processing is performed. CONSTITUTION:A selector circuit 11 executes a prescribed logical operation and generates generated polynominal information SD and a pseudo random code generation circuit 1 outputs pseudo random codes RP by a generated polynominal decided based on the generated polynominal information SD. An EX-OR gate 6 outputs scrambled output digital signals DO for which input digital signals DI are scrambled by receiving the input digital signals DI as one of input, receiving the pseudo random codes RP as the other input and calculating the exclusive OR of them. Thus, since the generated polynominal can be changed by a packet unit, the hardly decodable scramble processing can be performed.
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