| 摘要 |
<p>PURPOSE:To obtain logical level conversion circuit for a non-volatile memory capable of realizing a device in which a through current of a VPP system power supply is prevented and power consumption is reduced and which has a single power source of lower voltage. CONSTITUTION:A PMOS transistor M1 and a NMOS transistor M2 are connected in series between a VPP system power source and ground, a capacitor C for clamp is connected between gates of these transistors M1 and M2. And a PMOS transistor M3 which controls charging to the capacitor C and a PMOS transistor M4 which controls a current flowing into this transistor M3 are connected in series between a node 1 and the VPP system power source, and a logic signal D1 (n) of a logical level of the VCC system is applied to a node 2. While, a logical signal D0 (n) of a logical level of the VPP system of which a level is converted form a node 3 is introduced.</p> |
