| 摘要 |
PURPOSE:To provide the demodulator for a digital phase modulation signal whose reception sensitivity is improved when a reception level is lowered. CONSTITUTION:Input phases P1-Pn are compared with phase values delayed by a 1-symbol delay section 11 at a phase difference detection section 12, the phase difference value is protected by K number of stages at a protection section 13 and the result is imparted to an absolute value detection section 14, in which the phase difference is converted into an absolute value. A phase detection section 15 by pi/2 or over detects the absolute value of pi/2 or over, a DPLL section 16 extracts a demodulated 21kHz symbol clock and a demodulated 42kHz clock based on a detection signal, and a decode section 17 decodes a high-order 2-bit output from the protection section 13 to obtain demodulation data. The protection section 13 is provided with forward/backward K-stage protection sections 131, 132, K-stage protection is applied to the high- order 2-bit of the phase difference value to cancel noise and outputs from the forward/backward K-stage protection sections 131, 132 is inputted to the decode section 17. |
