| 摘要 |
A circuit for generating two internal clocking signals with non-overlapping phases at the frequency of an input external clock. A differentiator means receives a first digital signal and outputs a first digital pulse coupled to a first input of a flip-flop means, causing the flip-flop means to enter a first logic state. A first output of the flip-flop means is provided to an inverter means, which outputs a first internal clocking signal. A second output of the flip-flop means is provided to a second inverter means, which outputs a second internal clocking signal. A reset means is coupled to receive the second output of the flip-flop means and the output of the differentiator means. The reset means provides an output coupled to a second input of the flip-flop means, the reset means provides a second digital pulse in response to a transition in logic state of the second output of the flip-flop means when the flip-flop means enter the first logic state, thereby causing the flip-flop means to enter a second logic state.
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