发明名称 MULTIPLYING METHOD AND MULTIPLYING CIRCUIT
摘要 PURPOSE:To provide a multiplying method and a multiplying circuit capable of executing multiplication without expanding circuit size too much even when the bit length of data is extended by coding both of a multiplier and a multiplicand by using Booth algorithm. CONSTITUTION:A multiplier 1 and a multiplicand 2 are respectively inputted to Booth coding means 3, 4. Four 4-bit parts expressing the absolute values of four 5-bit signals out of code signals 5, 6 obtained by coding the multiplier 1 and code signals 7, 8 obtained by coding the multiplicand 2 are inputted to a partial product generating means 9 and partial products 14 to 17 are outputted from the means 9 and inputted to a partial product adding means 18. On the other hand, code bits 10 to 13 expressing the codes of the code signals 5 to 8 are also inputted to the means 18 to control the addition/subtraction of the partial products 14 to 17. Addition/subtraction is executed by the means 18 and a product 19 is outputted.
申请公布号 JPH06290029(A) 申请公布日期 1994.10.18
申请号 JP19930073164 申请日期 1993.03.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MINEMARU TAKAYUKI;TOYOKURA MAKI
分类号 G06F7/533;G06F7/52;G06F17/10 主分类号 G06F7/533
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