CONTROL LOGIC DEVICE

摘要

The control circuit for DMA (Direct Memory Access) preventing CPU halt during DMA operation to increase CPU utilization has the CPU (10) sending the DMA control signal to the DMA Controller (30) via the buffer (15). The CPU (10) sends the swap-out data to the buffer (20) which are to be saved in the hard disk or the floppy disk by the DMA Controller (30) in master mode. The DMA Controller (30) sends the swap-in data to the buffer (20) which are to be loaded into the main memory by the CPU (10).