| 摘要 |
forming a transistor consisting of a gate electrode, source and drain on a substrate, forming an interlevel insulating layer on the overall surface of the substrate, forming a first silicon layer on the interlevel insulating layer; selectively etching the first silicon layer, forming a thin insulating layer on the remaining first silicon layer; forming a second silicon layer on the thin insulating layer; etching the first silicon layer by a predetermined thickness, and at the same time, forming a silicon spacer on the sidewall of the first silicon layer, etching the exposed interlevel insulating layer using the first silicon layer and silicon spacer as a mask to expose the source, and at the same time, removing the remaining thin insulating layer, forming a third silicon layer on the overall surface of the substrate, forming a third silicon layer on the overall surface of the substrate, forming a dielectric layer on the surface of the charge storage electrode, and forming a plate electrode on the dielectric layer.
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