Circuit for the CSD [canonical signed digit] encoding of a binary two's complement or binary number

摘要

Digital circuit for the CSD encoding of a binary two's complement number or binary number which has no sign, in which the properties of the CSD code mean that two neighbouring bit positions cannot be occupied at the same time. Since the CSD code can be generated only recursively, it was deemed important for there to be a minimum delay for each bit position. The basic circuit has a delay time of one NOR gate for each bit position. An additional look-ahead logic unit, which is connected in parallel with the basic logic unit, reduces the delay time many times over. A look-ahead logic unit of any desired bit length requires a delay time of 2 NAND gates from the relevant input to the output. In an exemplary embodiment using a look-ahead length of 8 bits, it was possible to generate a 32-bit word in 15.5 NAND-gate delays and a 64-bit CSD code word in 23.5 NAND-gate delays, both in the context of tenable hardware expenditure. <IMAGE>