VARIABLE DYNAMIC DIVIDER CIRCUIT

摘要

The adjustable dynamic divider circuit includes first through fifth output means in parallel structured as a string NAND cell type to maintain a regular high-frequency clock signal and dividing control signal in a constant logic level by receiving them as a common signal of each gate terminal to repeatedly perform a turn On/Off operation, thus temporarily storing data in the capacitors; and a divider control signal which receives a plurality of control signals as a common control signal of each gate terminal according to a frequency dividing ratio determined by the peripheral circuit in accordance with the signals output from the first through fifth outputted means and then operates by dividing the first through fifth output means into divider 5 through divider 2 circuits.