PARTIAL BEAMFORMING

摘要

In accordance with the principles of the present invention, advantage is taken by the inventors of the fact that the speed of operation of the digital hardware in a digital beamformer can be reduced by providing, for example, multiple phases of the data signals and then processing the multi-phase data in N parallel summing paths. An interpolation-decimation filter receives the multi-phase data from the N parallel summing paths and provides at its output a signal having a reduced data rate (1/N). In accordance with this technique, the speed of operation of the individual digital circuits for forming the required beamforming delays is not increased as compared to conventional post-beamforming interpolation schemes, so that hereby the effective data rate is increased by a factor N and results in a decrease of the delay quantization error by a factor N. In accordance with the principles of the invention, the interpolation-decimation filter is incorporated into the beamformer at a most advantageous place. That is, it is incorporated into the beamformer processing after partial beamforming of a group of receive channels and before formation of the final beam. This approach allows the final beamforming to be simple and performed at a relatively low data rate and allows the higher rate signal processing to be confined to circuitry which may advantageously be on a single type of integrated circuit which is repetitively used in the beamformer.