DIGITAL BEAMFORMER HAVING MULTI-PHASE PARALLEL PROCESSING

摘要

In accordance with the principles of the present invention, advantage is taken by the inventors of the fact that the speed of operation of the digital hardware in a digital beamformer having a plurality of parallel receiving channels can be reduced by providing multiple phases for the data signals supplied by each receiving channel and then processing the multi-phase data in N parallel summing paths. An interpolation-decimation filter receives the multi-phase data from the N parallel summing phaths and provides at its output a signal having a reduced data rate (1/N). In accordance with this technique, the speed of operation of the individual digital circuits for forming the required beamforming delays are not increased as compared to conventional post-beamforming interpolation schemes, so that hereby the effective data rate is increased by a factor N and the delay quantization error is reduced by a factor N.