| 摘要 |
Integrated circuit chip-to-chip interconnections are made via gold pads (24, 34) on each chip (101, 102) that are bonded to corresponding gold pads (14, 12) on a silicon wafer chip carrier (10). The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature-- i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon carrier, and depositing the gold on the silicon dioxide layer. |
