| 摘要 |
A semiconductor memory device, that has a plurality of writing ports and reading ports comprises a first data latch portion, at least one second data latch portions, and communication units. The first data latch portion is directly accessible by externally entering an address signal, and the second data latch portions are parallel connected to the first data latch portion. The communication units is used to access one of the first and second data latch portions. Therefore, according to the semiconductor memory device of the present invention, the amount of hardware of a register file of the processor employing parallel processing and local register architecture can be significantly reduced by providing the first data latch portion and at least one or more of the second data latch portions having communication units and accessing one of the first and second data latch portions.
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