发明名称 |
Method and apparatus for avoiding deadlock in a computer system with two or more protocol-controlled buses interconnected by a bus adaptor |
摘要 |
A method and an apparatus to avoid a deadlock in a computer system with several busses connected by a bus adapter. If units of different busses of the computer system simultaneously start operations for which more than one bus is needed, it may come to a deadlock. By introducing a BUS SUSPEND signal to one of the busses and adapting the bus-protocol to honor this signal at distinct time slots, deadlock situations are avoided.
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申请公布号 |
US5355455(A) |
申请公布日期 |
1994.10.11 |
申请号 |
US19930171268 |
申请日期 |
1993.12.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HILGENDORF, ROLF B.;SCHLIPF, THOMAS |
分类号 |
G06F13/36;(IPC1-7):G06F13/14 |
主分类号 |
G06F13/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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